No clean flux composition and methods for use thereof

ABSTRACT

A flux formulation includes an activator and a protic solvent. The activator may be glutaric acid, levulinic acid, 2-ketobutyric acid, 2-oxovaleric acid, or mixtures thereof. Suitable protic solvents include alkanediol, alkoxy propanol and alkoxy ethanol. The flux formulation may be a no-clean flux formulation that may be used in the soldering of electronic circuit board assemblies, for example, in conjunction with a support fixture having a planar back surface that minimizes vibrations during processing that might otherwise cause misalignment between a chip and a substrate prior to solder reflow.

BACKGROUND

The present application relates generally to the manufacture ofmicroelectronic components, and more specifically to no clean fluxcompositions and methods for soldering, such as in the assembly ofintegrated circuit modules and integrated circuit boards.

During the manufacture of microelectronic components, electricalconnections are made, for example, between a single or multiple chipsand a substrate. In an example manufacturing process, a chip is soldereddirectly to a substrate such as a laminate. In such manufacturingprocesses, a soldering flux is typically used to help fuse the elementsbeing electrically connected. The soldering flux reacts with andeliminates surface oxides or impurities and protects the surfaces beingsoldered against further oxidation during soldering. The soldering fluxmay also improve wettability of the solder.

In a soldering process, solder bumps or metal pads on respectivecomponents to be joined are aligned and temporarily held in place with atacky soldering flux. During the subsequent reflow process, the assemblyis heated to melt the solder and form metallurgical bonds and electricalconnections. To improve reliability, an underfill material can be usedto fill the gap between the soldered components. The underfill materialdecreases the impact of thermal stresses that may otherwise compromisethe solder joint and/or fragile materials that are present within one ofthe components, such as low-k dielectric materials that are used withina chip.

Fluxes in use by the microelectronics industry for automated solderingof printed circuit assemblies typically contain corrosive organic acidsor components that, upon heating and dissipation of the flux, leave adecomposition residue that if un-cleaned will adversely impact adhesionof the underfill material to one or both of the components being joinedand may also negatively impact the electrical contact resistance acrossthe solder joint. Effective removal of such residue can be challengingin view of the narrow gap dimensions between the soldered components.Moreover, a step of residue removal adds time and expense to thesoldering process.

In view of the foregoing, it would be advantageous to provide a no cleanflux composition that does not require a cleaning process to remove fluxresidue from the device after reflow.

SUMMARY

In accordance with embodiments of the present application, a fluxformulation includes an activator and a protic solvent. The activatorcan be a diacid or a keto acid having a boiling, sublimation ordecomposition point of from 150° C. to 260° C. Example activatorsinclude glutaric acid, levulinic acid, 2-ketobutyric acid, 2-oxovalericacid, or mixtures thereof. Suitable protic solvents include alkanediol,alkoxy propanol and alkoxy ethanol. In embodiments, the flux formulationis a no-clean flux formulation that may be used in the soldering ofelectronic circuit board assemblies. An example flux formulationincludes 5-15 wt. % activator such as a diacid or keto acid, and 85-95wt. % protic solvent.

A soldering method involves applying the flux formulation to a surfaceof a first substrate to be soldered. The first substrate may include aplurality of solder bumps or metal contacts. The solder bumps or metalcontacts are then placed in contact with solder bumps formed on asurface of a second substrate and heated to melt the solder bumps andsolder the first substrate to the second substrate.

The first and second substrates may be a laminate substrate and a chip,for example. Further, to facilitate transport of the first and secondsubstrates, for example into and out of a soldering furnace, the firstand second substrates may be placed on a fixture such as a tray thatsupports the chip-substrate assembly. In embodiments, the fixture is analuminum tray having a planar backside surface. The planar backsidesurface is configured to maintain good thermo-mechanical contact with amoving belt that carries the fixture and parts to be soldered through asoldering furnace. Such good contact maintains the alignment of the chipto the substrate by minimizing the vibration of the chip-substrateassembly. The fixture enables the use of less viscous and tacky no cleanfluxes than conventional water-soluble fluxes.

In embodiments, the disclosed flux formulation is a no clean fluxformulation that may be incorporated into a soldering method involvingchips that contain low-k dielectric materials. The no clean fluxformulation enables an in-line underfill process that minimizesthermally-induced stresses and facilitates use of the low-k dielectricmaterials.

BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

The following detailed description of specific embodiments of thepresent application can be best understood when read in conjunction withthe following drawings, where like structure is indicated with likereference numerals and in which:

FIG. 1 is a thermo gravimetric analysis (TGA) scan for glutaric acid;

FIG. 2 is a schematic diagram of no clean flux soldering methodaccording to embodiments;

FIG. 3A is a cross-sectional schematic view of a semiconductor packageat a preliminary stage of packaging;

FIG. 3B is a cross-sectional schematic view of a semiconductor packageafter underfill is incorporated between the chip and the substrate;

FIG. 4 is an optical photograph of a conventional support fixture forsoldering semiconductor components;

FIG. 5A is an optical photograph of a support fixture for solderingsemiconductor components according to embodiments; and

FIG. 5B is an optical photograph of a support fixture for solderingsemiconductor components according to further embodiments.

DETAILED DESCRIPTION

Reference will now be made in greater detail to various embodiments ofthe subject matter of the present application, some embodiments of whichare illustrated in the accompanying drawings. The same referencenumerals will be used throughout the drawings to refer to the same orsimilar parts.

According to various embodiments, a flux formulation comprises anactivator and a protic solvent. The activator may comprise an organicacid such as a diacid or a keto acid. Diacids contain two carboxylicacid groups. Keto acids or ketoacids (also called oxo acids or oxoacids)are organic compounds that contain a carboxylic acid group and a ketonegroup. Exemplary organic acids include glutaric acid, levulinic acid,2-ketobutyric acid, 2-oxovaleric acid, or mixtures thereof. A thermogravimetric analysis (TGA) scan for glutaric acid is shown in FIG. 1.Initial decomposition of glutaric acid is seen at about 150° C. Theactivator is effective to remove oxides present from the surfaces to besoldered and improve wetting of a solder thereto.

A protic solvent includes an acidic hydrogen atom and can act as aproton (H⁺) donor. In various embodiments a protic solvent includes ahydrogen atom bound to an oxygen atom, as in a hydroxyl group. Exampleprotic solvents include alkanediols, alkoxy propanols, alkoxy ethanols,or mixtures thereof. Examples of alkanediols include 1,2-propanediol,1,3-propanediol, 1,2-butanediol, 1,3-butanediol, 1,4-butanediol,3-methyl-1,3-butanediol, 1,5-pentanediol, 3-methyl-1,5-pentanediol,1,2-hexanediol, 1,6-hexanediol, and 2-ethyl-1,3-hexanediol. Examples ofalkoxy propanols include 1-propoxy-2-propanol, propylene glycol n-butylether, di(propylene glycol) methyl ether, di(propylene glycol) propylether. Examples of alkoxy ethanols include 2-butoxy ethanol and 2-proxyethanol. In various embodiments, the flux formulation is a solution ofan organic acid dissolved in a protic solvent.

An example flux formulation comprises 5-15 wt. % (e.g., 5, 10 or 15 wt.%) activator and 85-95 wt. % (e.g., 85, 90 or 95 wt. %) protic solvent.A further example flux formulation consists essentially of 5-15 wt. %diacid or keto acid and 85-95 wt. % protic solvent. According toembodiments, the flux formulation does not include water and is free ofamine compounds. In particular, amine compounds typically formnon-volatile salts and are excluded from the disclosed fluxformulations. Further, the flux formulation according to embodimentsdoes not include halides or organic resins.

Each of the activator and the solvent has a boiling, sublimation ordecomposition point in the range of 150° C. to 260° C. such that bothcomponents substantially or completely evaporate or sublime duringsolder reflow and are not present after reflow. The disclosed fluxformulations remain tacky after application, and are adapted to hold analigned chip in position on a substrate prior to solder reflow. Thetackiness of the disclosed flux formulations may range from 20 to 120gram-force (gf) at 23° C., e.g., 20, 40, 60, 80, 100 or 120 gf,including ranges between any of the foregoing values. In embodiments,the activator and the solvent dissipate completely when heated to areflow temperature of 150° C. or above (e.g., 260° C.).

The substrate may comprise a semiconductor material such as silicon.Alternatively, the substrate may comprise an insulating material such asa glass and/or a polymer. For example, the substrate may be a printedcircuit board and comprise a glass epoxy. The substrate may include bondpad metallization structures, which can comprise Ni, Au, Cr, Cu, Ti, W,as well as combinations and alloys thereof.

The chip may comprise logic or memory functionality, for example. Inembodiments, the chip comprises a low-k dielectric material. As usedherein, a low-k dielectric material has a dielectric constant less thanthat of silicon oxide. For advanced node chips, decreasing thedielectric constant in the wiring layers is important for high-speeddata transmission.

Though the incorporation of low-k dielectric materials intosemiconductor device structures can provide a significant increase indevice performance, the porous nature of low-k dielectric materialstypically results in poor mechanical strength compared to traditionaldielectric films such as silicon oxide, which results in low overalltoughness and poor adhesion attributes. These attributes lead to achallenging set of mechanical issues during the packaging of chips thatcontain low-k dielectrics.

In particular, the coefficient of thermal expansion (CTE) mismatchbetween the silicon-based chip and the organic substrate (laminate)produces thermomechanical stresses that can lead to solder bump fatigue,delamination of the low-k dielectric materials, and even the failure ofthe electronic package. The chip may also include solder bumps forsoldering the chip to the metallization structures of the substrate.

The solder bumps may comprise lead (Pb) or, in embodiments, a lead-freesolder may be used. Example Pb-free solder compositions includetin-based solders such as tin-copper alloys. Tin-copper solders mayinclude trace amounts of silver, for example. The eutectic temperaturefor the binary tin-copper system is about 228° C.

Flip-chip assembly onto substrates using solder is typically performedby spraying or brushing a flux formulation onto the substrate. A fluxcan also be applied by dipping a chip into the flux. Flux formulationsdesirably possess a number of characteristics, including suitablerheology, solderability, and their compatibility with molded orcapillary underfill materials. The viscosity of the flux formulation,for example, should be high enough to avoid wicking and contamination ofthe chip, but low enough to be uniformly applied to the chip orsubstrate. An additional characteristic of a flux formulation is itsability to retain the flipped chip in position during reflow.

The principle function of a flux is to promote solderability(wettability) between two surfaces. During the soldering operation,after applying the flux formulation to the substrate, the chip and thesubstrate are aligned, brought into contact, and joined by heating theassembly to a temperature above the melting point (liquidus temperature)of the solder (i.e., solder reflow). In operation, the assembly may beconveyed over or through a pre-heater to evaporate the solvent andactivate the flux, and then conveyed into a furnace such as a convectionfurnace to affect melting of the solder. In operation, the furnace maycomprise a circulated, heated gas such as nitrogen (N₂) gas. The thermalprofile of an example reflow solder process is depicted in FIG. 2. Theillustrated process includes multiple stages, i.e., pre-heat, thermalsoak, reflow, in-line underfill, curing and cooling.

During the pre-heat, the temperature of the assembly is increased,typically at a heating rate of 1-3° C./sec to minimize thermal shock andavoid cracking. During the pre-heat, solvent from the flux formulationbegins to evaporate.

Optionally, as also shown schematically in FIG. 2, prior to the pre-heatcomponents of the assembly can be exposed to a surface-cleaning reducingplasma treatment. A reducing plasma may comprise, for example a mixtureof hydrogen with helium or argon or mixtures thereof. Hydrogen is usedas a reducing agent. An example reducing gas composition includes 1-5%hydrogen, with the balance being an inert carrier gas. In embodiments,the plasma treatment is performed at atmospheric pressure, which allowssurfaces to be treated continuously. In operation, according toembodiments, a workpiece (chip or substrate) is conveyed proximate to aplasma head in open air where the reducing plasma can reduce surface tinoxides of tin-based solders, for example.

Following the pre-heat, a thermal soak of typically 5 to 120 seconds maybe used to remove volatile components and activate the flux. During thethermal soak, the activator begins to reduce oxides that are present onmetal pads and solder balls. A thermal soak temperature of 100° C. to200° C. may be used. Too high a temperature may lead to solderspattering or oxidation, while the flux formulation may not adequatelyactivate if the temperature is too low. The thermal soak can alsominimize temperature gradients across the assembly and, in embodiments,establish a thermal equilibrium between the chip, solder and substrateprior to solder reflow.

During the soak, the flux reacts with and dissipates metal oxides andoptionally other contaminants present on the metal surfaces to be joinedto produce clean metal surfaces. This allows for the formation ofintermetallic compounds that create a strong bond between the solder andthe adjacent metal. In embodiments, evaporation of the solvent anddissipation of metal oxides leaves no residue on the substrate or on thechip.

During solder reflow, the maximum temperature of the process is reached.A common reflow temperature is 20° C. to 40° C. above the liquidustemperature of the solder. A reflow time (e.g., time at temperature) mayrange from 5 to 90 seconds. The term “reflow” is used to refer to aprocess where the solder undergoes a solid-to-liquid phasetransformation (as opposed to merely softening). During reflow, the fluxdecreases surface tension at the interface between the solder and themetallization structures, which facilitates metallurgical bonding whenthe solder melts. Too high a reflow temperature or too much time attemperature may induce damage to the chip or substrate, while too low areflow temperature or too little time at temperature may result intrapped solvent or flux, or the formation of cold joints or voids.

After solder reflow, the assembly is gradually cooled to solidify thesolder joints. Proper cooling minimizes excess intermetallic formationand thermal shock to the components. The cooling rate may range from 5to 10° C./second.

In order to minimize the stress across solder joints, and as explainedin further detail below, an underfill material may be introduced to thechip-substrate assembly during cooling of the assembly. Application ofan underfill material may be performed at 100 to 120° C., e.g., 110° C.Underfilling may be performed in-line, i.e., during the cooling cyclefrom the reflow temperature without cooling the assembly to below 100°C. until after the underfill is added.

In embodiments, a flip-chip assembly is formed by soldering the solderbumps of an integrated circuit chip to the appropriate metal bond sitesof a substrate. The reflow soldering operation typically leaves a gap of0.02 mm to 0.2 mm between the chip and the substrate. The gap may befilled with an underfill material, which in embodiments may be dispensedaround the periphery of the soldered structure and allowed to flowbetween the chip and the substrate by capillary action.

The underfill material is adapted to relieve thermomechanical stresseson the solder interconnections that arise due to the difference incoefficients of thermal expansion (CTE) between the silicon-based chip(CTE 2.5×10⁻⁶/° C.) and the organic substrate (CTE˜15-20×10⁻⁶/° C.). Theuse of lead-free solders, which are harder than lead-containing solders,exacerbates the build up of such thermomechanical stresses.

As seen also with reference to FIG. 2, prior to applying the underfillmaterial, exposed surfaces within the gap may be treated with anoxidizing plasma. The oxidizing plasma may eliminate flux residue, andotherwise promote good adhesion of the underfill material.

After its application the underfill material may be partially or fullycured within a temperature range of from greater than 100° C. to 130°C., e.g., 120° C. In embodiments, the temperature of the chip-substrateassembly is maintained above 100° C. between the reflow and underfillcure. After solder reflow, the underfill material may be fully cured ina separate process if desired. In addition to minimizing process-inducedtemperature gradients, this approach decreases total process time.

Typical underfill materials include epoxy resins, curing agents andinorganic fillers that form a cross-linked thermosetting polymer whencured. The properties of the cured polymer, such as the CTE and elasticmodulus, decrease the thermomechanical stress on the solder joints andalleviate stresses that would otherwise be transferred into the IC chip.

Once cured, the underfill acts as a buffer between the chip and thesubstrate and functions to distribute the CTE-induced stress over theentire or substantially entire interfacial surface of the chip.Underfill materials also protect the interconnects from moisture andother forms of contamination.

According to various embodiments, FIG. 3A is schematic cutaway view of asemiconductor package 300 at an initial stage of packaging. Initially, aflux formulation is applied to a chip side of substrate 310. The fluxformulation may be applied by spray coating, for example, to metal pads(not shown) formed on the substrate.

Chip 220 including a low-k dielectric layer 221 is attached to thesubstrate 310 by reflowing solder associated with a plurality of solderballs 320 that may be formed in an array on the chip 220. Acorresponding array of metal pads is disposed on the substrate 310 sothat when the solder balls 320 are reflowed, the solder bonds to thepads of the substrate 310, thereby electrically connecting the solderballs 320 to the pads. During reflow soldering, the chip and substrateare heated until the solder balls 320 are in a liquid state.

After the chip 220 is electrically attached to the substrate 310, a gap250 is formed between adjacent surfaces of the chip 220 and thesubstrate 310. Though the solder balls 320 bridge the gap 250, the gap250 is not total filled.

Interlayer dielectrics such as low-k dielectric layer 221 that areincorporated into the chip 220 are subject to cracking if excess stressis exerted on the chip 220. A capillary underfill 350, however,generally minimizes the force exerted on the chip 220 and thereforeminimizes the risk of stress-induced cracking within the chip 220.Underfill 350 can be applied using several methods known to thoseskilled in the art.

FIG. 3B is schematic cutaway view of a semiconductor package 300 after acapillary underfill 350 has been placed between the chip 220 and thesubstrate 310. Underfill 350 effectively strengthens the bonded chip 220by distributing the forces exerted on the chip via the reflowed solderover a larger area.

In embodiments, the chip-substrate assembly is held and transported by afixture such as a tray that carries the assembly through the variousstages of the soldering process. Shown in FIG. 4 is a photograph of aconventional fixture 400 that is configured to carry typically 4-32chip-substrate assemblies. Fixture 400 includes a frame 410 definingopen areas 420. Each open area 420 comprises a plurality of peripheraltabs 430 that are adapted to cooperatively support a chip-substrateassembly within each respective open area 420. Open areas 420 allow aheated gas such as heated nitrogen gas to flow over a large surface areaof the assembly. During use, fixture 400 may be mounted onto a conveyorsuch as a belt or chain.

The contact area of fixture 400 with the belt is designed to be small sothat the efficiency of heating the chip-substrate assemblies with gas ismaximized But such a smaller contact area can cause a greater vibrationof the chip-substrate assemblies due to the belt vibration and movement.The greater vibrations can be overcome with a viscous and tacky flux,which inhibits or prevents misalignment of the chip from its substrate.

A fixture 500 according to embodiments is shown in FIG. 5A and 5B. Theillustrated fixture 500 is a monolithic tray constructed of a metal suchas aluminum. The fixture 500 includes a frame 510 defining substantiallyclosed areas 520. Closed areas 520 are recessed from a top surface ofthe frame 510 and include a support surface 522 for supporting achip-substrate assembly. One or more apertures 524 are formed in eachsupport surface 522. Apertures 524 allow a heated gas to circulate overa backside of a chip-substrate assembly that is supported by supportsurface 522.

Support surface 522 may be a planar surface as depicted in FIG. 5A.Alternatively, support surface 522 may comprise one or more raisedridges 526 as depicted in FIG. 5B. Raised ridges 526 are configured tosupport a chip-substrate assembly, defining a fluid channel between thesupport surface and the substrate. Heated gas can flow into the fluidchannel via one or more apertures 524.

Fixture 500 includes a planar backside surface opposite to supportsurface 522. During operation, in various embodiments, the planarbackside surface makes contact with a conveyor belt, i.e., over a largefraction of the surface area of the backside surface. For instance, atleast 25% (e.g., 25, 30, 50, 75, 80, 85, 90, 95, 97 or 99%, includingranges between any of the foregoing values) of the backside surfacemakes direct physical contact with a surface of the conveyor belt whileless than 20% of the backside contacts a reflow furnace belt in aconventional fixture. The large area contact between the fixture and theconveyor belt dampens vibrations due to motion of the belt that mightotherwise cause misalignment between a chip and a substrate prior tosolder reflow. Thus the presently-disclosed fixtures enable the use of aless viscous and tacky flux, which can in turn evaporate more easily asa no clean flux.

As used herein, the singular forms “a,” “an” and “the” include pluralreferents unless the context clearly dictates otherwise. Thus, forexample, reference to a “solder bump” includes examples having two ormore such “solder bumps” unless the context clearly indicates otherwise.

Unless otherwise expressly stated, it is in no way intended that anymethod set forth herein be construed as requiring that its steps beperformed in a specific order. Accordingly, where a method claim doesnot actually recite an order to be followed by its steps or it is nototherwise specifically stated in the claims or descriptions that thesteps are to be limited to a specific order, it is no way intended thatany particular order be inferred. Any recited single or multiple featureor aspect in any one claim can be combined or permuted with any otherrecited feature or aspect in any other claim or claims.

It will be understood that when an element such as a layer, region orsubstrate is referred to as being formed on, deposited on, or disposed“on” or “over” another element, it can be directly on the other elementor intervening elements may also be present. In contrast, when anelement is referred to as being “directly on” or “directly over” anotherelement, no intervening elements are present.

While various features, elements or steps of particular embodiments maybe disclosed using the transitional phrase “comprising,” it is to beunderstood that alternative embodiments, including those that may bedescribed using the transitional phrases “consisting” or “consistingessentially of,” are implied. Thus, for example, implied alternativeembodiments to a flux formulation that comprises an activator and aprotic solvent include embodiments where a flux formulation consistsessentially of an activator and a protic solvent and embodiments where aflux formulation consists of an activator and a protic solvent.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the present inventionwithout departing from the spirit and scope of the invention. Sincemodifications, combinations, sub-combinations and variations of thedisclosed embodiments incorporating the spirit and substance of theinvention may occur to persons skilled in the art, the invention shouldbe construed to include everything within the scope of the appendedclaims and their equivalents.

1.-10. (canceled)
 11. A soldering method comprising: exposing a firstsubstrate to a reducing plasma at a temperature from 20° C. to 25° C.;applying a flux formulation comprising an activator and a proticsolvent, wherein the activator is a ketoacid having a boiling,sublimation or decomposition point of from 150° C. to 260° C. onto asurface of the first substrate to be soldered, the surface of the firstsubstrate comprising a plurality of first solder bumps or metalcontacts, contacting second solder bumps disposed on a surface of asecond substrate to be soldered with the first solder bumps or metalcontacts, and heating the first solder bumps or metal contacts and thesecond solder bumps to a first temperature to solder the first solderbumps or metal contacts to the second solder bumps and form a solderedassembly.
 12. (canceled)
 13. The method of claim 11, wherein the firsttemperature is 150° C. to 260° C.
 14. The method of claim 11, furthercomprising cooling the soldered assembly to a second temperature andapplying an underfill material between the first substrate and thesecond substrate at the second temperature, wherein the secondtemperature is 100° C. to 120° C.
 15. The method of claim 14, furthercomprising exposing the soldered assembly to an oxidizing plasma priorto applying the underfill material.
 16. The method of claim 14, furthercomprising curing the underfill material at a third temperature greaterthan the second temperature.
 17. The method of claim 11, furthercomprising placing the first substrate on a top surface of a fixtureprior to the contacting, wherein the fixture has a planar bottom surfaceopposite to the top surface.
 18. The method of claim 17, wherein theplanar bottom surface comprises at least 25% of an area of the fixture.19. The method of claim 17, wherein the first substrate is placed into arecessed region formed in the top surface.
 20. The method of claim 17,wherein the fixture comprises a plurality of apertures extending throughthe fixture from the first surface to the second surface.
 21. The methodof claim 1, wherein the ketoacid is selected from the group consistingof 2-ketobutyric acid, 2-oxovaleric acid and mixtures thereof.
 22. Themethod of claim 1, wherein the flux formulation does not containhalides.
 23. The method of claim 1, wherein the flux formulation doesnot contain halides or organic resins.
 24. A soldering methodcomprising: providing a first substrate comprising a plurality of firstsolder bumps or metal contacts affixed to a surface thereof; exposingthe surface of the first substrate to a reducing plasma at a temperaturefrom 20° C. to 25° C.; applying a flux formulation comprising anactivator and a protic solvent, wherein the activator is a diacid orketoacid having a boiling, sublimation or decomposition point of from150° C. to 260° C. onto a surface of the first substrate; contacting thefirst solder bumps or metal contacts disposed on a surface of the firstsubstrate to a second substrate, and heating the first solder bumps ormetal contacts to a first temperature to solder the first solder bumpsor metal contacts to the second substrate to form a soldered assembly.25. The method of claim 24, wherein the reducing plasma compriseshydrogen.
 26. The method of claim 24, further comprising cooling thesoldered assembly to a second temperature and applying an underfillmaterial between the first substrate and the second substrate at thesecond temperature, wherein the second temperature is 100° C. to 120° C.27. The method of claim 26, further comprising exposing the solderedassembly to an oxidizing plasma prior to applying the underfillmaterial.
 28. The method of claim 26, further comprising curing theunderfill material at a third temperature greater than the secondtemperature.
 29. The method of claim 24, wherein the activator is aketoacid selected from the group consisting of 2-ketobutyric acid,2-oxovaleric acid and mixtures thereof
 30. The method of claim 24,wherein the flux formulation does not contain halides or organic resins.